Design issues of an asynchronous parallel fuzzy processor

The paper presents the design of a VLSI fuzzy processor which is capable of performing fuzzy inferences based on the α-level sets theory. The use of the α-level sets family to represent fuzzy sets allows a considerable saving of memory resources if compared with conventional fuzzy inference methods which use membership functions to represent fuzzy sets. The main features of the architecture presented are parallelism and scalability. The processor comprises a set of units which work parallelly and asynchronously to process the various rules. The structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. The performance obtainable is about 310 KFLIPS, with a clock frequency of 60 MHz, 8 input variables, either crisp or fuzzy, and an 8-bit resolution