High performance chip to substrate interconnects utilizing embedded structure

A high performance packaging approach for state-of-the-art high frequency ICs has been adopted by creating fully planar Au-Cu-Au carrier-interconnect surfaces for the embedded chip(s) on low dielectric constant i.e. low k substrates using innovative wafer processing techniques. A mixture of coplanar and microstrip solution for interconnects has been introduced and modified e-gun, sputtering and liftoff steps used to create high quality surfaces in order to lower the losses for high speed, high frequency ICs for communication systems. A number of ICs fabricated in different technologies may be embedded in a MCM-module with interconnect design rules similar to that of IC-technologies using the techniques introduced in this paper