Optimizing C4 bump placements for a peripheral I/O design

In this paper we are going to describe how to place N number of I/O bumps using C4 technology along the edge of the die for optimum die size and bump placement. At Intel most of the I/O bumps for C4 interconnect are placed along the edge of the die. For typical products at Intel there are about 350 I/O bumps that one needs to place along the edge of the die. These I/O bumps have to be placed under the following constraints: 1. minimize impact to the die size. This requires understanding the I/O cell area on the silicon and the best aspect ratio of the I/O cell consistent with the C4 package design rules. 2. Minimize the number of the package routing layers