Integrated circuit packaging with laminated microinterconnect

Author

Chen, Y. Kevin ; Egbert, William C. ; Kane, Didier ; Schultz, John C.

Author_Institution

Fiber Opt. & Electron. Technol. Center, 3M Co., St Paul, MN, USA

fYear

1999

fDate

1999

Firstpage

266

Lastpage

271

Abstract

The integrated circuit package is a major cost and performance factor in high I/O count, high-speed integrated circuit packaging. 3M´s Laminated MicroInterconnect (LMI) technology provides a unique solution for polymer based IC packaging using flip-chip or anisotropic conductive adhesive attachment. The basic LMI construction is discussed and contrasted with more conventional built-up multilayer approaches. Example design rules and routing capabilities are presented in the context of a 900 I/O, 35 mm IC packaging test vehicle. Environmental performance of this integrated circuit package with daisy chain and Kelvin structure test vehicles are also reviewed

Keywords

flip-chip devices; high-speed integrated circuits; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; microassembling; network routing; 35 mm; Kelvin structure test vehicle; anisotropic conductive adhesive attachment; daisy chain structure test vehicle; flip-chip attachment; high speed IC packaging; laminated microinterconnect; micro-via substrate; polymer based IC packaging; routing capabilities; Anisotropic magnetoresistance; Circuit testing; Conductive adhesives; Costs; High speed integrated circuits; Integrated circuit packaging; Integrated circuit technology; Integrated circuit testing; Polymers; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1999. 1999 Proceedings. 49th

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

0-7803-5231-9

Type

conf

DOI

10.1109/ECTC.1999.776183

Filename

776183