Title :
300 megabit/second Berlekamp decoder for binary BCH codes
Author_Institution :
AT&T Bell Lab., Naperville, IL, USA
Abstract :
A very fast, parallel, combinatorial Berlekamp decoder that can perform the second step in binary BCH decoding at rates exceeding 300 Mb/s is presented. The circuit given is for the t=3 case. It is possible to build a t=5 decoder that can operate faster than 100 Mb/s. In addition to the Berlekamp section, the complete BCH decoder also requires a syndrome generator and a root finder. These can be implemented in a straightforward way with sequential circuits and ROMs or fast static RAMs. For the t=3 code, there are only three syndrome components yielding 48 clock cycles for 255 incoming bits
Keywords :
BCH codes; binary sequences; decoding; digital circuits; 300 Mbit/s; ROM; binary BCH codes; combinatorial Berlekamp decoder; digital circuits; fast static RAM; root finder; sequential circuits; syndrome generator; Decoding; Delay; Error correction codes; Galois fields; Hardware; Logic circuits; Polynomials; Read only memory; Table lookup; Very large scale integration;
Conference_Titel :
Global Telecommunications Conference, 1991. GLOBECOM '91. 'Countdown to the New Millennium. Featuring a Mini-Theme on: Personal Communications Services
Conference_Location :
Phoenix, AZ
Print_ISBN :
0-87942-697-7
DOI :
10.1109/GLOCOM.1991.188488