Title :
Fast, dense, predictable and 100% routable MACH 3 and 4 family
Author_Institution :
Programmable Logic Div., Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
This paper focuses on the silicon architecture of AMD´s second generation Macro Array CMOS High Speed/High Density (MACH) family of PLDs. Implemented with an advanced 0.65 μm technology and driven strongly by customer needs MACH 3 and 4 family is optimized for speed, predictability, density, flexibility and 100% routability. The major thrusts for the family are to allow the following: design changes without changing pinouts, 100% routability. Flexible PAL blocks, synchronous/asynchronous flexible macrocells with built-in XOR capability and up to 20 product terms of logic without any incremental delay, flexible set/reset and clocking control and 5 V in-circuit programmability with IEEE 1149.1 JTAG interface in 100-208 pins PQFP packages. MACH 3 and 4 family is designed to offer fixed, predictable worst-case pin-to-pin delays of 15 ns and external systems clock frequency up to 50+ MHz
Keywords :
CMOS logic circuits; logic design; network routing; programmable logic devices; 0.65 micron; 100% routability; 15 ns; 5 V; 50 MHz; AMD; CMOS high speed ICs; IEEE 1149.1 JTAG interface; MACH 3; MACH 4; MACH device family; Macro Array; PLDs; PQFP packages; Si; Si architecture; asynchronous flexible macrocells; built-in XOR capability; flexible PAL blocks; high density chips; second generation devices; synchronous flexible macrocells; Character generation; Clocks; Delay; Logic arrays; Macrocell networks; Packaging; Pins; Programmable logic arrays; Programmable logic devices; Switches;
Conference_Titel :
WESCON/94. Idea/Microelectronics. Conference Record
Conference_Location :
Anaheim , CA
Print_ISBN :
0-7803-9992-7
DOI :
10.1109/WESCON.1994.403525
