Fast parallel implementation of H.264 /AVC transform exploiting SIMD instructions

This paper presents a fast parallel implementation of H.264 transform (FPU) using SIMD instructions. The block size of transform used by H.264 is 4 x 4, which is quite different to the transform of the previous video compression documentations. The 4 x 4 transform is computed in integer arithmetic and can avoid the mismatch of inverse transform. The transform is very low computational, because it just uses additions and shifts, without multiplications. However, it is hard to using SIMD instructions to optimize the transform because the 4 x 4 block can not use the 16 -byte register efficiently. This paper gives out a solution to use SIMD instructions efficiently and designs a fast transform of H.264. Simulation result reveals that the FPIT using SIMD instructions increases up to 13 -15 times comparing to the same data by using fast transform in butterfly structure [2][3]onP4 2.0 GHZ.