A high level design solution for FPGA´s

Recently, the density of FPGA´s has increased to complexities rivalling gate array technology. It is predicted that by the end of 1995, FPGAs exceeding 60 thousand equivalent gates, with clock speeds up to 100 MHz will be available for designers. It is also predicted that the cost per gate of FPGAs will drop to three times that of ASICs around 1995 as compared to 20 times in 1985. All these factors, combined with the time to market advantages of FPGAs, will make FPGA technology more attractive to designers who currently utilize traditional ASIC technologies. The introduction of Altera´s EPF8050M, an MCM with 50,000 usable gates provides a solution that directly addresses engineers´ ASIC prototyping needs. Powerful design tools will enable the transition to FPGAs from ASICs by addressing the increasing design complexity. High level design tools need to achieve good quality of results in resource utilization, and circuit performance, while also providing for high productivity through ease of use, predictability of results and tool performance. Advances in FPGA technology, coupled with improvement in design tools, will enable designers to achieve faster time to market for their system designs. This paper presents a high level design solution for the design of FPGA´s using logic synthesis technology. The high level design flow starts from a hardware description language and completes with physical implementation. The Synopsys FPGA Compiler will be presented as an example of advances in design tool technology