System design considerations for FPGA synthesis

Author

Olsen, Glenn

Author_Institution

Device Technol., MINC Inc., Colorado Springs, CO, USA

fYear

1994

fDate

27-29 Sep 1994

Firstpage

592

Lastpage

595

Abstract

This article provides an overview of some of the system level considerations when designing with FPGA/CPLD devices. The tools supporting these types of designs vary widely in the features that have a significant impact on the time and effort it takes to complete a design. With flexibility as the key, you should ensure your tools support a “top-down design” approach, have mixed mode (language and schematic) entry, and are integrated into a tool which can provide timing simulation and board layout. Finally, you should realize that CPLD devices now have a unique combination of speed and density that can potentially be used in areas where only FPGAs were considered viable

Keywords

circuit analysis computing; field programmable gate arrays; hardware description languages; high level synthesis; programmable logic devices; timing; CPLD; FPGA synthesis; board layout; density; mixed mode entry; speed; system design considerations; timing simulation; top-down design; Design engineering; Design methodology; Field programmable gate arrays; Job design; Logic design; Logic devices; Logic functions; Printed circuits; Signal design; Technology management;

fLanguage

English

Publisher

ieee

Conference_Titel

WESCON/94. Idea/Microelectronics. Conference Record

Conference_Location

Anaheim , CA

ISSN

1095-791X

Print_ISBN

0-7803-9992-7

Type

conf

DOI

10.1109/WESCON.1994.403531

Filename

403531