Getting the best from an FPGA via logic synthesis

FPGA designers face two significant challenges. First, how to capitalize on all those programmable gates in a timely fashion, given that a 5K gate part is about the biggest device that can be designed efficiently using traditional, schematic-based approaches. Second, how to get the best functionality and performance out of the devices when used in the context of the rest of the devices on the board or in the system. This paper concentrates on the role logic synthesis plays in helping designers achieve optimal designs across multiple FPGA architectures, without sacrificing results in any one device type. The overall top-down FPGA design flow is also addressed, including language-based design, multilevel simulation, design retargeting (e.g., to or from ASICs) and device physical implementation