Chip scale package implementation challenges

Author

Ghaffarian, Rem

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1999

fDate

1999

Firstpage

619

Lastpage

626

Abstract

The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of test vehicles. We also discuss the most current package isothermal aging to 2000 hours at 100°C and 125°C and thermal cycling test results to 1700 cycles in the range of -30 to 100°C

Keywords

ageing; chip scale packaging; integrated circuit reliability; integrated circuit testing; life testing; production testing; quality control; -30 to 100 degC; 100 degC; 125 degC; 2000 hr; Consortium CSP test vehicles; chip scale package; microvia boards; package isothermal aging; quality; reliability; test vehicles; thermal cycling test results; Assembly; Buildings; Chip scale packaging; Costs; Flip chip; Testing; Vehicles; Wafer bonding; Wafer scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1999. 1999 Proceedings. 49th

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

0-7803-5231-9

Type

conf

DOI

10.1109/ECTC.1999.776244

Filename

776244