36 bit wide FIFO for deep, bus oriented applications

Speciality memories, such as FIFO devices, derive their high performance from their architecture as well as their underlying technology. The need for higher speed in FIFO devices has resulted in the introduction of faster and faster devices, with access times as low as 10 ns, such as the QS7204-10. Nevertheless, traditional FIFO interfaces, even at the 10 ns access time level, fall short of meeting today´s leading edge CPU performance requirements. Clocked interfaces allow better utilization of the memory bandwidth and can provide data rates of 66 MHz and beyond in real world system environments. High speed, 36 bit wide FIFO devices, packaged in the fine pitch TQFP package, enable high performance, high density system designs. This paper focuses on three aspects of FIFO devices: speed, word depth, and additional value added features to show how these enhancements can boost system performance and board efficiency