The effects of clamping diodes on signal integrity

This paper discusses the so called kickback effect associated with the clamping diodes or ESD circuits of buffers used in high speed digital systems. Based on the lab tests and simulations reported here, it was determined that the kickback effect is caused by the unique clamping characteristics of the CMOS buffers and can be explained through the laws of transmission line theory. The diffusion capacitance of a clamping diode is only an amplifying factor in the mechanism of the kickback effect, increasing the amplitude of the bump to higher levels. In general terms, in order to avoid the kickback effect, buffers should not have clamping currents on their outputs at smaller negative voltages than the clamping voltages of the diode on the far end of the transmission line. Bipolar or BiCMOS buffers or buffers with p-channel MOSFET pulldown transistors satisfy this requirement, but raising the anode voltage of the clamping diode to about +700 mV will also achieve good results. Traditional methods, such as careful impedance matching between the buffer and its loading transmission line can also be used as a solution for the problem