Vlsi Systolic Array Implementation Of A Staged Decoder For Bcm Signals

Author

Caire, G. ; Ventura-Traveset, J. ; Murphy, J. ; Kung, S.Y.

Author_Institution

Princeton University

fYear

1992

fDate

28-30 Oct 1992

Firstpage

139

Lastpage

149

Keywords

Bandwidth; Binary codes; Block codes; CMOS technology; Decoding; Hardware; Signal design; Systolic arrays; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, V, 1992., [Workshop on]

Print_ISBN

0-7803-0811-5

Type

DOI

10.1109/VLSISP.1992.641046

Filename

641046

Link To Document