Synthesizing finite state machines for minimum length synchronizing sequence using partial scan

The goal is to synthesize an FSM with the objective to minimize the number of scanned flip-flops while requiring a minimum number of system clocks to reach the synchronizable state. An algorithm for selecting state variables for scanning while minimizing the length of the synchronizing sequence based on the reverse-order-search technique is presented. Extra transitions may be required to avoid possible lock-in conditions if the initial state is an invalid state for the machines where the number of states is not a power of 2. Experimental results show that the proposed method guarantees synchronizability and testability through the proper state assignment with reasonable hardware overhead for the benchmark circuits.<>