DocumentCode
2937566
Title
Process-Tolerant Ultralow Voltage Digital Subthreshold Design
Author
Roy, Kaushik ; Kulkarni, Jaydeep P. ; Hwang, Myeong-Eun
Author_Institution
Purdue Univ., West Lafayette, IN
fYear
2008
fDate
23-25 Jan. 2008
Firstpage
42
Lastpage
45
Abstract
We propose process variation tolerant circuit techniques for robust digital subthreshold design. We present an 8times8 process-tolerant FIR filter, working in both super-threshold and subthreshold regions featuring adaptive beta-ratio modulation and integrated level converters. Ultra-dynamic voltage scaling (UVDS) enables the filter operation at 85 mV consuming 40 nW. For memory applications, we propose Schmitt trigger based SRAM bitcell exhibiting built-in process variation tolerance. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.
Keywords
CMOS digital integrated circuits; FIR filters; tolerance analysis; CMOS technology; SRAM bitcell; Schmitt trigger; adaptive beta-ratio modulation; integrated level converters; process variation tolerant circuit techniques; process-tolerant FIR filter; process-tolerant ultralow voltage design; robust digital subthreshold design; size 0.13 mum; ultra-dynamic voltage scaling; voltage 160 mV; CMOS technology; Circuits; Dynamic voltage scaling; Finite impulse response filter; Frequency; Inverters; MOS devices; Random access memory; Robustness; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on
Conference_Location
Orlando, FL
Print_ISBN
978-1-4244-1855-8
Electronic_ISBN
978-1-4244-1856-5
Type
conf
DOI
10.1109/SMIC.2008.17
Filename
4446251
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