65nm SOI CMOS SoC Technology for Low-Power mmWave and RF Platform

Author

Kim, Daeik D. ; Kim, Jonghae ; Cho, Choongyeun ; Plouchart, Jean-Olivier ; Trzcinski, Robert

Author_Institution

Semicond. R&D Center, IBM, Hopewell Junction, NY

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

46

Lastpage

49

Abstract

An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to f_T=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.

Keywords

CMOS analogue integrated circuits; capacitors; delay circuits; inductors; invertors; low-power electronics; millimetre wave field effect transistors; millimetre wave oscillators; phase locked loops; silicon-on-insulator; system-on-chip; FET performance; NFET; PFET; PLL front-end components; SOI CMOS SoC technology; frequency 200 GHz; frequency 300 GHz; inverter stage delay; low-power RF platform; low-power mmWave platform; phase locked loop; ring oscillator; size 65 nm; vertical native capacitor; CMOS technology; Capacitors; Delay; FETs; Inductors; Parasitic capacitance; Phase noise; Q factor; Radio frequency; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on

Conference_Location

Orlando, FL

Print_ISBN

978-1-4244-1855-8

Electronic_ISBN

978-1-4244-1856-5

Type

conf

DOI

10.1109/SMIC.2008.18

Filename

4446252