LDO EMC susceptibility modeling with on-chip sensor measurements

Low-dropout voltage regulator (LDO) is widely used in up-to-date electrical systems but with severe EMC problems. Its susceptibility prediction has become one of the major concerns both of IC suppliers before fabrication to avoid redesign cost and customers before real application to reduce incompatible. This paper presents a LDO susceptibility modeling study including IEC standard modeling flow and immunity test applied to a dedicated test chip. Two on-chip voltage sensors are used to characterize the radio frequency interference propagation inside LDO and thus validate the susceptibility modeling process.