An outboard processor for high performance implementation of transport layer protocols

The high throughputs promised by emerging network technologies are often difficult to achieve application-to-application because of host transport protocol bottlenecks. The authors describe an experimental prototype implementation of an outboard protocol processor which eliminates these bottlenecks by performing transport layer functions in dedicated hardware. The architecture consists of separate transmit and receive CPUs, each with checksum and direct memory access circuits. Measurements made using an implementation of the TCP protocol indicate that this architecture can support end-to-end throughputs in excess of 11000 packets/s between UNIX hosts. One of the aims is to use this processor to determine the most appropriate techniques for transport of data on high speed metropolitan area networks