DocumentCode

2938511

Title

Early footprint comparison for area I/0 packages and first level interconnect

Author

Hirt, E. ; Troster, G.

Author_Institution

Electronics Lab, ETH Zurich

fYear

1999

fDate

1-4 June 1999

Firstpage

1210

Lastpage

1216

Keywords

Assembly; Bonding; Chip scale packaging; Electronics packaging; Flip chip; Integrated circuit packaging; Manufacturing; Space technology; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1999. 1999 Proceedings. 49th

Conference_Location

San Diego, CA, USA

ISSN

0569-5503

Print_ISBN

0-7803-5231-9

Type

conf

DOI

10.1109/ECTC.1999.776380

Filename

776380