High-Speed Parallel Architecture for Software-Based CRC

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called ´N-byte RCC (Repetition of Computation and Combination)´´. This algorithm is the iterative process of message computation by the ´slicing-by-4´ and combination through the ´zero block lookup tables´. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the ´slicing-by-8´ which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.