Title :
Fabrication process of copper lead frame chip scale package (LF-CSP)
Author :
Moon, Jong Tae ; Hong, Sung Hak ; Yoon, Seung Wook ; Park, Chang Jun ; Choi, Yoon Hwa ; Kim, Jae Myun ; Lee, Jong Hyun ; Kim, Ja Ryoung ; Koh, Yo Hwan
Author_Institution :
Device Res. Dept., Hyundai Electron. Co., Inchon, South Korea
Abstract :
In this study, a new packaging technique employing the copper LF-CSP was developed for memory devices. The technique is expected to be lower in production cost and better electrical performance compared with conventional packaging technique. In this paper, the simulation results on the electrical and thermal performance of the package, assembly process, selection of the UBM materials, and reliability of the LF-CSP are presented. In addition, the cost estimation of the LF-CSP was made in comparison with the conventional packaging technologies
Keywords :
chip scale packaging; copper; integrated circuit economics; integrated circuit manufacture; integrated circuit reliability; integrated memory circuits; lead bonding; reflow soldering; thermal analysis; Cu; Cu lead frame CSP; UBM materials; assembly process; chip scale package; electrical performance; fabrication process; manufacturing cost estimation; memory devices; production cost; reliability; thermal performance; Chip scale packaging; Copper; Costs; Electronic packaging thermal management; Electronics packaging; Fabrication; Flip chip; Lead; Rapid thermal processing; Semiconductor device packaging;
Conference_Titel :
Electronic Components and Technology Conference, 1999. 1999 Proceedings. 49th
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5231-9
DOI :
10.1109/ECTC.1999.776395
