The University of Pennsylvania integrated circuit design environment

Over the last few years the High Energy Engineering Group at the University of Pennsylvania have successfully designed and fabricated a number of large analog and mixed analog/digital ICs. Most of these ICs have been fabricated in the 2.0 and 1.2 micron processes available through MOSIS, but some have gone directly to foundries like AT&T, UTMC, and IBM. In order to carry out this ambitious design effort a significant amount of time have been spent on developing and maintaining a full-custom and standard cell design environment at Penn. This environment currently consists of a fully characterized 50 leaf cell scalable standard cell library integrated with the Verilog simulator with back-annotation, as well as all the tools to design full custom analog and mixed signal ICs. Emphasis has been placed on full-chip post-layout simulations as well as other physical design verification techniques which yield a high first pass success rate. This payer will describe the design framework at Penn which allows a complete design process from conceptual design and high level behavioral simulation all the way through final post-layout simulations. The joint Penn/Cadence standard cell characterization effort will also be described