A 128-channel digital pipeline chip for silicon strip detector read-out

A digital VLSI device for silicon-strip detector read-out has been developed which supports 128 channels as well as providing amplifier calibration signals. This device provides buffering for 256 machine cycles of the hit-pattern of the strips as sensed by multi-channel amplifier/discriminator chips. A second-level buffer is provided. Testability, and alignment features are also provided. The device has been manufactured in a radiation hardened CMOS process. The power demand is 0.21 mW per channel at normal operating conditions. Maximum operating frequency is above 60 MHz. Layout takes into consideration detector geometry, so that mosaic placement of chips can be used to provide electronics pitch no larger than detector strip pitch, down to 45 microns. Serial control and read-out is implemented, to allow optical fiber communication with the controller. Use of dual-ported RAM for the pipeline implementation provides zero-dead-time acquisition. Signal levels to and from the chip are minimized for low noise operation