PMChip: an ASIC dedicated to pipelined read out and trigger systems

Author

Lai, Adriano ; Musa, Luciano

Author_Institution

Dipartimento di Fisica, Cagliari Univ., Italy

Volume

2

fYear

1994

fDate

30 Oct-5 Nov 1994

Firstpage

711

Abstract

We describe a custom VLSI circuit, which is the main component of the read out system for some of the detectors of the NA48 experiment at the CERN SPS. Such a readout system is conceived to be completely dead time free and is based on a pipelined architecture. Our ASIC contains an 8k circular memory, where data from ADC cards are stored continuously and can be retrieved after the time needed by the global trigger to make its decisions. It also contains a 256 locations output buffer for triggered data. The whole memory control logic has been integrated inside the ASIC. The VLSI approach allows to implement a number of very useful features which could not be possible on a discrete component system

Keywords

VLSI; application specific integrated circuits; detector circuits; high energy physics instrumentation computing; nuclear electronics; pipeline processing; trigger circuits; ASIC; CERN SPS; NA48 experiment; PMChip; custom VLSI circuit; memory control logic; pipelined architecture; pipelined read out; trigger systems; Application specific integrated circuits; Buffer storage; CMOS technology; Clocks; Data acquisition; Detectors; Logic; Pipelines; Random access memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference, 1994., 1994 IEEE Conference Record

Conference_Location

Norfolk, VA

Print_ISBN

0-7803-2544-3

Type

conf

DOI

10.1109/NSSMIC.1994.474511

Filename

474511