DC free runlength-limited codes

DC-free runlength-limited codes are studied. Their finite state sequential machine is defined and the achievable rate region is discussed. For the code construction aspect, two general rules are proposed as follows: (1) Always leave suitable redundancy when using the output word which is false in decreasing the running digital sum (RDS) in the absolute value. (2) If state splitting is inevitable, then first try to split the states with small n-l (where n and l are the accumulated RDS and encoding delay, respectively) and with large delay l. By using these rules, several DC-free (d,k) codes are constructed. It is shown that, by following the general rules, the trial work can be substantially reduced