Parallel implementation of motion-compensation for HDTV video decoder

Author

Lee, Charng L.

Author_Institution

Comput. & Commun. Res. Lab., Ind. Technol. Res. Inst., Chutung, Taiwan

fYear

1997

fDate

2-4 Dec 1997

Firstpage

51

Lastpage

54

Abstract

A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder

Keywords

decoding; digital signal processing chips; digital television; high definition television; integrated circuit layout; motion compensation; network routing; parallel architectures; television standards; video signal processing; 4:2:0 chroma format; 4:2:2 chroma format; 4:4:4 chroma format; HDTV video decoder; access delay; block layer memory modules; block layer picture partitioning; control scheme; decoding engines; interconnection network; macroblock structures; memory access conflicts; motion-compensation; parallel implementation; routing module; routing network; Communication industry; Decoding; Delay; Discrete cosine transforms; HDTV; Motion compensation; Parallel processing; Routing; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 1997. ISCE '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-4371-9

Type

conf

DOI

10.1109/ISCE.1997.658349

Filename

658349