A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection

This paper presents a high-resolution time-to-digital converter (TDC) for all-digital frequency synthesizer applications. This TDC achieves sub-gate delay resolution by a multipath ring oscillator (MRO). Also, seamless cycle detection is adopted to have compact hardware structurw. To optimize the timing resolution and power efficiency, an improved system model is developed for MRO design. The prototype chip uses a 90nm CMOS technology with a single 1.2-V supply voltage. Measurement results indicate that, under the loop setting for a 5GHz, -95dBc/Hz inband phase noise frequency synthesizer, the TDC covers the input 18.9ns dynamic range, 5.6ps timing resolution, with 0.23pJ/code power efficiency.