An efficient configurable hardware implementation of fundamental multirate filter banks

Efficient multimedia communications rely on real-time implementations of multirate filter banks. In this paper, we describe a field programmable gate array (FPGA) implementation of the analysis and synthesis filter banks which are the fundamental components of multirate systems. The implementation utilizes parallel distributed arithmetic which enables maximum exploitation of the parallelism inherent in the multirate filtering operation. Performance results suggest that the FPGA platform is indeed attractive for implementing multirate filter banks.