A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications

Author

Chang, Chia-Ming ; Chen, Yu-Jung ; Lu, Yen-Chang ; Lin, Chun-Yi ; Chen, Liang-Gee ; Chien, Shao-Yi

Author_Institution

Grad. Inst. of Networking & Multimedia, Nat. Taiwan Univ. Taipei, Taipei, Taiwan

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

405

Lastpage

408

Abstract

A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor is designed and implemented for mobile multimedia applications. It is fabricated in 65nm CMOS technology with core size of 7.56mm². The buffer bridged scheduler, energy efficient transaction technique and approximated rendering scheme are proposed to efficiently utilize energy to deliver excessive graphics rendering performance of 1.2Gvertices/s and 2.4Gpixels/s for 3D graphics applications. Moreover, configurable filtering unit (CFU) is also employed for accelerating image processing. Compared with state-of-the-art image signal processors (ISPs), 1.1 times to 7.2 times performance can be achieved by the proposed mobile graphics processor with CFU.

Keywords

CMOS digital integrated circuits; graphics processing units; image processing; mobile communication; multimedia communication; CFU; CMOS technology; ISP; approximated rendering scheme; buffer-bridged scheduler; configurable filtering unit; energy-efficient scalable eight-core 3D graphic processor; energy-efficient transaction technique; graphic rendering performance; image processing; image signal processors; mobile graphic processor; mobile multimedia applications; power 172.6 mW; size 65 nm; Computer architecture; Energy efficiency; Finite impulse response filter; Graphics processing unit; Mobile communication; Rendering (computer graphics);

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123602

Filename

6123602