Title :
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier
Author :
Akita, Ippei ; Furuta, Masanori ; Matsuno, Junya ; Itakura, Tetsuro
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between channels thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each channel. The proposed dynamic T/H amplifier enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14mm2 and the ADC consumes 36mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an Figure of Merit (FoM) of 300 fJ/conv. is achieved.
Keywords :
CMOS analogue integrated circuits; amplifiers; analogue-digital conversion; buffer circuits; sample and hold circuits; CMOS technology; FoM; SFDR; SNDR; dynamic T/H amplifier; dynamic track-and-hold amplifier; figure of merit; high-speed low-power operation; reference voltage buffer; signal-to-noise-and-distortion ratio; size 65 nm; spurious-free dynamic range; time-interleaved SAR ADC; voltage 1.2 V; word length 7 bit; CMOS integrated circuits; Capacitance; Capacitors; Frequency measurement; Power demand; Switches; Timing;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
DOI :
10.1109/ASSCC.2011.6123603
