A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation

A Time-Interleaved (TI) pipelined-SAR ADC with on-chip offset cancellation technique is presented. The design reuses the SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time. A 6 bit capacitive DAC is built as a flip-around MDAC for low inter-stage gain implementation. The capacitive attenuation solutions in both 1^st and 2^nd DACs minimize the power dissipation and optimize conversion speed. Measurements of a 65nm CMOS prototype operating at 160MS/s and 1.1V supply show 2.72mW total power consumption. The SNDR is 55.4dB and the FoM as low as 35fJ/conv.-step.