A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques

This paper presents a pipelined 32 bit sub-threshold adder in a 90nm CMOS technology that combines MHz-performance with sub-pJ energy consumption. To increase variation-resilience various circuit techniques are proposed, such as sub-threshold adapted transmission gate logic, optimal sizing for noise margins and time borrowing. These techniques enable operation down to a supply of 190mV at 10MHz and an energy consumption of 0.4 pJ per addition. A performance of 30 MHz is obtained at a supply of 260mV and 0.6 pJ per addition. The adder achieves an improvement in Energy-Delay Product of a factor 900 compared to the state-of-the-art sub-threshold adder design.