A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access

Author

Kushida, K. ; Hirabayashi, O. ; Tachibana, F. ; Hara, H. ; Kawasumi, A. ; Suzuki, A. ; Takeyama, Y. ; Fujimura, Y. ; Niki, Y. ; Shizuno, M. ; Sasaki, S. ; Yabe, T.

Author_Institution

Center for Semicond. R&D, Toshiba Corp. Semicond. Co., Kawasaki, Japan

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

161

Lastpage

164

Abstract

A low power SRAM operating at the logic supply voltage of 0.5V-1.0V without chip by chip trimming has been developed. A Dynamic Cell Stability Monitor controls wordline level adaptively by sensing the data flip in reference memory cells. The cell failure rate in every process corner is improved. A Modulated Wordline Level Scheme for Replica Cell optimizes sense timing and the operating frequency is improved by 18% at 1.0V. A Multiple Memory Cell Access Mode pushes the minimum operating cell supply voltage down to 0.5V. A 40nm 2Mb SRAM test chip with 0.24um² cell has demonstrated 0.5V operation.

Keywords

SRAM chips; low-power electronics; SRAM test chip; cell failure rate; chip trimming; data flip sensing; dynamic cell stability monitor; high density SRAM macro; logic supply voltage; low power SRAM; modulated wordline level scheme; multiple memory cell access mode; replica cell; size 40 nm; storage capacity 2 Mbit; trimless wide voltage operation; voltage 0.5 V to 1.0 V; Arrays; Circuit stability; Monitoring; Random access memory; System-on-a-chip; Timing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123627

Filename

6123627