• DocumentCode
    2941273
  • Title

    Low power cross-point memory architecture

  • Author

    Bateman, Bruce ; Siau, Chang ; Chevallier, Christophe

  • Author_Institution
    Unity Semicond. Corp., Sunnyvale, CA, USA
  • fYear
    2011
  • fDate
    14-16 Nov. 2011
  • Firstpage
    173
  • Lastpage
    176
  • Abstract
    Design techniques are described for building cross-point resistive memory arrays without the use of a selection device for each resistive memory element. A memory cell selection technique is shown to allow the use of low voltage transistors and to solve IR drop, electro-migration and disturb issues on the selected array lines. Physical implementation is also presented.
  • Keywords
    CMOS memory circuits; electromigration; integrated circuit design; low-power electronics; transistors; CMOS memory cell; IR drop; cross-point resistive memory array line; electromigration; low power cross-point memory architecture; low voltage transistor; memory cell selection technique; resistive memory element; Logic gates; Low voltage; Memory management; Metals; Microprocessors; Programming;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4577-1784-0
  • Type

    conf

  • DOI
    10.1109/ASSCC.2011.6123630
  • Filename
    6123630
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2941273