A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.