DocumentCode :
2942800
Title :
A design method of DWT analog neuro chip for VLSI implementation
Author :
Kamio, Takeshi ; Adachi, Haruyasu ; Ninomiya, Hiroshi ; Asai, Hiroki
Author_Institution :
Dept. of Syst. Eng., Shizuoka Univ., Hamamatsu, Japan
Volume :
2
fYear :
1997
fDate :
19-21 May 1997
Firstpage :
1210
Abstract :
Discrete Walsh transform (DWT) is one of the most important techniques as well as the discrete Fourier transform (DFT) in the field of signal processing. We have proposed the 8-bits DWT neuro chip based on Hopfield linear programming neural networks, which keeps the error less than 1% and carries out the DWT within 30 nano-seconds. In this paper, we show an effective design method of a DWT analog neural processor which is obtained by using the 8-bits DWT neural networks as modules
Keywords :
CMOS analogue integrated circuits; Hopfield neural nets; VLSI; Walsh functions; circuit CAD; linear programming; transforms; 30 ns; CMOS; Hopfield linear programming neural networks; VLSI implementation; analog neural processor; analog neuro chip; discrete Walsh transform; modules; signal processing; simulation; structural modularity; Circuit simulation; Design methodology; Discrete Fourier transforms; Discrete wavelet transforms; Hopfield neural networks; Integrated circuit interconnections; Linear programming; Neural networks; Signal processing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Instrumentation and Measurement Technology Conference, 1997. IMTC/97. Proceedings. Sensing, Processing, Networking., IEEE
Conference_Location :
Ottawa, Ont.
ISSN :
1091-5281
Print_ISBN :
0-7803-3747-6
Type :
conf
DOI :
10.1109/IMTC.1997.612391
Filename :
612391
Link To Document :
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