Generalized mergeability in space compressor design in built-in self-test of VLSI circuits

Author

Das, Sunil R. ; Barakat, Tony ; Nayak, Amiya R. ; Assai, M.H.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

2

fYear

1997

fDate

19-21 May 1997

Firstpage

1448

Abstract

In this paper, we establish a generalized mergeability criteria for merging an arbitrary number of output sequences under conditions of stochastic independence of line errors. This result extends previously known mergeability criteria for merging pairs of output sequences. We also provide preliminary simulation results on combinational benchmark circuits

Keywords

VLSI; built-in self test; combinational circuits; data compression; design for testability; logic design; logic testing; performance evaluation; stochastic systems; VLSI circuits; built-in self-test; combinational benchmark circuits; generalized mergeability criteria; line errors; output sequences; simulation results; space compressor design; stochastic independence; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computer science; Merging; Read only memory; Stochastic processes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 1997. IMTC/97. Proceedings. Sensing, Processing, Networking., IEEE

Conference_Location

Ottawa, Ont.

ISSN

1091-5281

Print_ISBN

0-7803-3747-6

Type

conf

DOI

10.1109/IMTC.1997.612439

Filename

612439