A novel wafer-yield PDF model and verification with 90–150nm SOC chips

Author

Masuda, Hiroo ; Tsunozaki, Manabu ; Tsutsui, Toshikazu ; Nunogami, Hiroyuki ; Uchida, Akihisa ; Tsunokuni, Kazuyuki

Author_Institution

Renesas Technol. Corp., Tokyo

fYear

2007

fDate

15-17 Oct. 2007

Firstpage

1

Lastpage

5

Abstract

In this paper, we describe a new wafer yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.

Keywords

integrated circuit modelling; integrated circuit yield; process monitoring; system-on-chip; SOC chips; effective defect density; production process lines; size 90 nm to 150 nm; spatial dependency; wafer edge defect; wafer yield distribution model; wafer-yield PDF model; yield loss; Density measurement; Electronics industry; Mathematical model; Monitoring; Poisson equations; Probability density function; Production; Semiconductor device measurement; Semiconductor device modeling; Statistical distributions;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1523-553X

Print_ISBN

978-1-4244-1142-9

Electronic_ISBN

1523-553X

Type

conf

DOI

10.1109/ISSM.2007.4446784

Filename

4446784