DocumentCode
2943769
Title
Yield prediction techniques based on DFM rules and criticality for 65nm technology and beyond
Author
Kojima, Tsutomu ; Kyou, S. ; Murakami, H. ; Honda, K. ; Nakayama, T. ; Matsuoka, F.
Author_Institution
Toshiba Corp., Yokohama
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
1
Lastpage
4
Abstract
Recently, various techniques of DFM (design for manufacturing) have suggested as counter measure of yield degradation. In this paper we focused on a design rule which causes yield and device degradation, and extracted a new rule with small process margins. In addition, we evaluated the systematic failure caused by small process margin, and defined the criticality as the function of its layout design rule. We describe the techniques that designer can not only predict yield degradation, but also recognize how critical the design rules are. The Techniques enable the productions to avoid complexity of design rule and to be competitive and mainstream in the industry.
Keywords
design for manufacture; electronics industry; semiconductor device manufacture; design for manufacturing; size 65 nm; yield prediction technique; Counting circuits; Degradation; Design for manufacture; Large scale integration; Manufacturing industries; Manufacturing processes; Paper technology; Production; Pulp manufacturing; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
978-1-4244-1142-9
Electronic_ISBN
1523-553X
Type
conf
DOI
10.1109/ISSM.2007.4446785
Filename
4446785
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