A new block-based design methodology and CAD toolset for mixed signal ASIC design

With the continuing trends towards smaller, faster and more complex chips, there is an ever increasing need for new CAD tools and methodologies to support the reuse of larger building blocks, i.e., move from current cell-based methodologies and tools to higher level macro-block and mega-cell based designs. This paper presents a CAD toolset that supports both top-down design methodology (partitioning, floorplanning and synthesis), and bottom-up electrical and physical implementation (e.g. transistor sizing, block characterization, and layout generation) for block-based mixed signal ASIC designs