Statistical multi-objective optimization and its application to IC layout design for E-Tests

The ultimate goal of design for manufacturing (DFM) should be a high final yield rather than just a precise reproduction of patterns. To achieve the high yield, this paper is to investigate the effects of the rounding corners, resulting from patterning, on the electrical tests (E-tests) and to determine the optimum layout design such that multiple E-test parameters can attain their desired values simultaneously. Statistical model building and optimization methods are developed and applied to achieve this goal. An actual design layout problem will be used to demonstrate and validate the proposed methods.