Transistor operations in 30-nm-gate-length EJ-MOSFETs

Author

Kawaura, H. ; Sakamoto, T. ; Baba, T. ; Ochiai, Y. ; Fujita, J. ; Matsui, S. ; Sone, J.

Author_Institution

Fundamental Res. Labs., NEC Corp., Tsukuba, Japan

fYear

1997

fDate

23-25 June 1997

Firstpage

14

Lastpage

15

Abstract

Discusses fabrication of electrically variable shallow junction MOSFETs (EJ-MOSFETs) to investigate transistor characteristics in ultra-fine gate MOSFETs. By using electron beam (EB) lithography and an ultra-high resolution resist (Calixarene), we could achieve a gate length of 30 nm for the first time. Since the short-channel effects are effectively suppressed by electrically induced ultra-shallow source/drain regions in the structure, the fabricated device exhibited normal transistor characteristics in the 30-nm-gate-length regime at 300 K.

Keywords

MOSFET; characteristics measurement; electron resists; semiconductor technology; 30 nm; 300 K; Calixarene; EJ-MOSFETs; electrically variable shallow junction MOSFETs; electron beam lithography; gate length; ultra-fine gate devices; ultra-high resolution resist; ultra-shallow source/drain regions; Boron; Electron beams; Laboratories; Lithography; MOSFETs; National electric code; Resists; Silicon; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 1997. 5th

Conference_Location

Fort Collins, CO, USA

Print_ISBN

0-7803-3911-8

Type

conf

DOI

10.1109/DRC.1997.612456

Filename

612456