Experimental and analytical studies on CMOS scaling in deep submicron regime including quantum and polysilicon gate depletion effects

Author

Kai Chen ; Chenming Hu ; Peng Fang ; Gupta, A. ; Ming Pen Lin ; Wollesen, D.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1997

fDate

23-25 June 1997

Firstpage

20

Lastpage

21

Abstract

To study CMOS scaling and develop analytical equations to predict future CMOS performance with device and voltage scaling in deep submicron regime, MOSFETs and CMOS ring oscillators fabricated with 2.5 to 6nm T/sub ox/, and channel length down to 0.2/spl mu/m were characterized at 1.5 to 3.3V to confirm the analytical expressions for I/sub dsat/ and gate delay. Based on the experimental and analytical investigation on the fabricated MOSFETs and ring oscillators with wide ranges of T/sub ox/ and L/sub eff/ at various V/sub dd/, I/sub dsat/ and t/sub pd/ can be accurately modeled and predicted from the electrical oxide thickness and universal mobility model.

Keywords

CMOS integrated circuits; MOSFET; ULSI; delays; elemental semiconductors; integrated circuit measurement; integrated circuit modelling; silicon; 1.5 to 3.3 V; 2.5 to 6 nm; CMOS scaling; Si; channel length; deep submicron regime; electrical oxide thickness; gate delay; polysilicon gate depletion effects; ring oscillators; universal mobility model; voltage scaling; Degradation; Electric variables measurement; Equations; MOS devices; MOSFETs; Performance analysis; Predictive models; Propagation delay; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 1997. 5th

Conference_Location

Fort Collins, CO, USA

Print_ISBN

0-7803-3911-8

Type

conf

DOI

10.1109/DRC.1997.612459

Filename

612459