A sensitive technique to enable technology transfer and fab matching in deep sub-micron technologies

Author

Wang, Bin ; Paulsen, Ron

Author_Institution

Impinj Inc., Seattle

fYear

2007

fDate

15-17 Oct. 2007

Firstpage

1

Lastpage

4

Abstract

A sensitive floating-gate integrator technique using single-poly pFET NVM technology has been developed and utilized to enable technology transfer and improved fab matching of logic NVM designs in a standard logic CMOS process. With utilization of our technique, an abnormal parasitic RC relaxation phenomenon observed in a floating gate design was effectively characterized across six foundries and from 0.35 mum to 90 nm logic CMOS technologies. The technique is used as a powerful tool to debug manufacturing issues and to monitor the manufacturability of advanced technologies.

Keywords

CMOS integrated circuits; field effect transistors; deep sub-micron technologies; fab matching; logic NVM designs; sensitive floating-gate integrator technique; sensitive technique; single-poly pFET NVM technology; standard logic CMOS process; technology transfer; CMOS logic circuits; CMOS technology; Dielectric measurements; Foundries; Logic circuits; Logic design; Manufacturing processes; Monitoring; Technology transfer; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1523-553X

Print_ISBN

978-1-4244-1142-9

Electronic_ISBN

1523-553X

Type

conf

DOI

10.1109/ISSM.2007.4446836

Filename

4446836