Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology

CMOS devices are being scaled for density and speed. However, scaling gate length is impeded by lithographic technology and scaling device width is limited by low hole mobility in PMOS transistors. In vertical MOS transistors, however, lithography does not limit the channel length. Current drive in PMOS devices may also be increased by use of a SiGe channel. In fact, the hole mobility in strained SiGe normal to the growth plane is predicted to be significantly larger than in its unstrained counterpart. Therefore, we propose vertical Si/sub 1-x/Ge/sub x//Si PMOS and Si NMOS transistors and demonstrate (1) 100% increase of drive current in a vertical SiGe PMOS device, (2) the first experimental evidence of the enhancement of out-of-plane hole mobility in a vertical PMOSFET, and (3) experimental results for vertical NMOS devices, thus exhibiting the promise of vertical SiGe/Si CMOS.