DocumentCode
2944743
Title
Study on process control limits for super junction fabrication by simulation with robust design
Author
Kuramochi, N. ; Oomuro, Y. ; Tokano, K.
Author_Institution
TOSHIBA, Kawasaki
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
1
Lastpage
4
Abstract
Quality engineering study on the estimation of process control limits for the manufacturing super junction structure is presented. Experimental conditions were allocated to the L36 orthogonal array. Breakdown voltage and on-resistance were calculated with TCAD and the signal to noise ratio (SN ratio) for each condition was obtained. Effect of each control factor was investigated in the main effect plot for the SN ratio and control limits were determined to satisfy the specific limits. Novel approach to the numerical estimation is also presented.
Keywords
integrated circuit manufacture; process control; L36 orthogonal array; PC-P-009; process control limits; quality engineering; robust design ISSM paper; signal to noise ratio; super junction fabrication; Boron; Epitaxial growth; Epitaxial layers; Fabrication; Ion implantation; Microelectronics; P-n junctions; Process control; Robust control; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
978-1-4244-1142-9
Electronic_ISBN
1523-553X
Type
conf
DOI
10.1109/ISSM.2007.4446840
Filename
4446840
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