DocumentCode
2945212
Title
Spacer etch optimization on high density memory products to eliminate core leakage failures
Author
Dharmarajan, Easwar ; Song, Shengnian ; Mclaughlin, Lenore ; Guan, John ; Gazda, Jerzy ; Lin, Emma ; Qi, Wen-Jie ; Shiraiwa, Hidehiko ; Hussey, James ; Lansford, Jeremy ; Banerjee, Basab
Author_Institution
Spansion LLC, Austin
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
1
Lastpage
4
Abstract
Through this work, we present a core leakage failure mechanism in our 90 nm high density memory products which was found to be related to etch process loading sensitivity to high density. Process optimization was done to fix the problem while maintaining sufficient etch margin against stringers.
Keywords
etching; flash memories; integrated circuit manufacture; leakage currents; core leakage failures; etch process loading sensitivity; high density memory circuits; process optimization; size 90 nm; spacer etch optimization; Cobalt; Current measurement; Density measurement; Etching; Failure analysis; Flash memory; Manufacturing industries; Silicides; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
978-1-4244-1142-9
Electronic_ISBN
1523-553X
Type
conf
DOI
10.1109/ISSM.2007.4446867
Filename
4446867
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