DocumentCode
2945580
Title
Dynamic defect-limited yield prediction by criticality factor
Author
Svidenko, Vicky ; Shimshi, Rinat ; Nehmadi, Youval
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
1
Lastpage
4
Abstract
In this paper, we present a new methodology for inline yield prediction based on defect inspection and design data. We derive a new metric called criticality factor (CF), which is essentially a fractional critical area for a defect of the reported size in a small layout window around the reported defect location. CF would be a good predictor of yield if geometrical considerations alone determined whether an electrical fail will result. Since other properties of the defect affect the electrical outcome (such as material properties), we employ a Training Set of wafers where the functional relation between CF and die yield is learned for each critical inspection step. From that point on these curves are used to predict the yield impact of in-line defects for new wafers. In addition, we show that highly-systematic defects (i.e. layout dependent) deviate from the CF functional curves, and hence add noise to the calculation. We suggest a technique to separate these defects from the random population, and calculate a corrected CF value for them.
Keywords
integrated circuit layout; integrated circuit technology; integrated circuit yield; critical inspection; criticality factor; defect inspection; design data; die yield; dynamic defect-limited yield prediction; inline yield prediction; training set; Inspection; Integrated circuit modeling; Integrated circuit yield; Manufacturing processes; Material properties; Predictive models; Production; Sampling methods; Semiconductor device modeling; Semiconductor device noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
978-1-4244-1142-9
Electronic_ISBN
1523-553X
Type
conf
DOI
10.1109/ISSM.2007.4446887
Filename
4446887
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