Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications

A cost effective bit-plane coder with throughput enhancement in JPEG2000 applications is proposed. Many papers and the results of chip implementation show that memory requirement dominates the hardware cost of the bit-plane coder. In order to reduce the memory size, a memory-free algorithm is proposed to eliminate state variable memories by calculating three coding state variables (γ_p+1[n], σ_p+1[n], and π_p[n]) on the fly. We also propose a stripe-column-based pass-parallel operation to perform three coding passes in pipeline operation and to encode four samples within the stripe-column concurrently for the high throughput requirement. Experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures because of the proposed memory-free algorithm. Furthermore, the proposed architecture has 3 times greater throughput than other familiar architectures.